1. Technical Field
The present invention pertains generally to the field of integrated circuits. More specifically, certain embodiments relate to the testing of buffer circuits on integrated circuits.
2. Background Art
Contemporary schemes for verifying operation of an integrated circuit (IC) include I/O loopback testing for an input/output (I/O) buffer circuit of the IC. I/O loopback tests are typically carried out by driving data through an output component of an I/O buffer circuit of the IC, subsequently driving associated data back through an input component of the same I/O buffer circuit, and verifying whether the input data and output data correctly correspond to one another. Such I/O loopback testing aids in evaluation of whether the input and output components of the I/O buffer circuit are functioning properly.
As integrated circuit (IC) features continue to shrink, test costs relentlessly increase. Greater numbers of interface nodes, higher operating frequencies, and specialized packaging arrangements such as multi-chip modules all contribute to soaring test costs. To avoid wasting packaging materials and assembly costs, some tests are performed on an integrated circuit die prior to package assembly. Equipment for testing integrated circuits before assembly increases in cost and complexity as die contacts decrease in size and increase in number. Indeed, the cost of exhaustive pre-assembly testing of every interface node of an integrated circuit is becoming prohibitive. Unfortunately, saving costs by reducing pre-assembly testing translates into increasing post-assembly waste.
The number of I/O pins in the interfaces of upcoming generations of memory devices is expected to increase—e.g. from about 30 pins in some current dynamic random access memory (DRAM) devices to around 512-1024 DQ pins and around 8 channels of address and command pins. Even if all such pins could be probed during a wafer probe, it would be cost prohibitive for direct automatic test equipment (ATE) wafer probe testing. Moreover, wafer probe ATE and probe tooling are limited to about 500 MHz clock rates, which corresponds to 1 giga-transfers per second (1 GT/s) for double data rate (DDR) circuit testing. However, future memory devices are forecast to reach up to about 2 giga-transfers per second (GT/s) performance capability. For at least these reasons, the current state of the art for IC testing is inadequate for upcoming generations of devices.